1. Field of the Invention
This invention relates to a novel metal interconnect structure for use with integrated circuit devices in the formation of integrated circuit structures, and a process of making same. More particularly, this invention relates to a metal interconnect structure formed on a first substrate and then bonded to a second substrate which contains integrated circuit devices, and a process for making such structures.
2. Description of the Related Art
In the construction of VLSI integrated circuit structures, the formation of the active devices on/in the semiconductor substrate such as a silicon wafer involves the formation of multiple insulation and conductive layers, as well as temporary masking layers, and can involve numerous processing steps, including deposition, masking, doping, and etching steps. If a problem should arise during one of the processing steps which cannot be remedied, all of the previous processing steps may be adversely impacted, which can add considerably to the cost of the individual integrated circuit dies eventually obtained from the processed wafer, i.e., by lowering the yield. In addition, once the individual integrated circuit devices, such as MOS and bipolar transistors, are formed on/in the semiconductor substrate, they must be electrically connected or "wired" to other devices to form the desired electrical circuitry comprising the integrated circuit structure, i.e., additional processing steps must be performed to construct the "wiring" structure.
Furthermore, while previous simpler structures might have only required a single layer of metal interconnects between bonding pads on the surface of the chip or die and the individual connections to the elements of each active device, e.g., the source, drain, and gate electrodes of an MOS transistor, it is not uncommon for three or four or more metal interconnect layers to be utilized with VLSI integrated circuit structures. This, in turn, requires separation of each layer of metal interconnects from adjacent metal layers using insulating layers through which openings or vias are selectively cut and then filled with metal to provide electrical connections, when needed, between the metal interconnects on one layer and metal connects on an adjacent layer. Complete filling of such openings with metal and the formation of metal to metal bonding between the metal in the opening and the underlying and overlying metal interconnects to insure electrical connection therebetween has created further problems.
Thus, even when the individual integrated circuit devices are flawlessly constructed on and in the semiconductor substrate, a mistake or problem occurring during the construction of the metal interconnect layers can result in damage to the structure which will result in the need to salvage the entire substrate or wafer, or at least increase the defect rate of chips formed from each such substrate or wafer, i.e., reduce the yield. It would, therefore, be highly desirable to separate or segregate the construction of the metal interconnect layers from the prior construction of the integrated circuit devices in and on the semiconductor substrate.
In the past, structures have been proposed or built wherein one or more chips were mounted to a multilayer ceramic structure having a series of metal interconnects formed on each ceramic layer to thereby electrically interconnect, for example, a series of individual chips to form the desired electrical circuit. Such a multilayer ceramic mounting structure also served as a heat dissipating medium for the heat generated during the operation of each individual chip.
However, such ceramic bases or mounting pads were bulky and cumbersome and did not lend themselves to incorporation into the individual packaging of the integrated circuit chip or die itself, but rather served, at least in some instances, merely as a heat dissipating printed circuit mounting board to which a series of integrated circuit chips were mounted.
It would, therefore, be advantageous to provide a separate construct for the metal interconnect layers used to electrically connect the individual integrated circuit (semiconductor) devices formed on a semiconductor substrate to form the desired integrated circuit structure comprising the chip or die.